1. Field of the Invention
The present invention relates to an information processing apparatus employing a computer, and particularly to an improvement of a data length deciding circuit of the information processing apparatus which employs instructions involving different data lengths.
2. Description of the Related Art
To improve data processing efficiency, an information processing apparatus employs instructions which operate on data of different lengths (byte length data, word length data, etc.). To correctly operate the information processing apparatus, it is necessary to correctly transfer and write instructions which operate on data whose length are proper for respective internal elements of the information processing apparatus. To decide the length of each data to be operated on by each instruction, a data length deciding circuit is employed. Recent increased functionality requirements for computer systems result in the need for high-speed decision capabilities and reduced circuit scale for the data length deciding circuit.
There are two conventional techniques for deciding the data length of an instruction. One is to directly specify the data length in the instruction program. The other is not only to directly specify the data length according to a microprogram of the instruction, but also to indirectly specify the data length according to an instruction code.
The former technique directly writes data length information of an instruction in a microprogram of the instruction. This technique expands the size of the program to increase the required capacity of a memory such as a ROM for storing the program.
The latter technique inserts a code indicating the data length of an instruction in a microprogram for the instruction itself, and stores actual data length information corresponding to the code in a separate table. When the code in the microprogram is read, an address in the table corresponding to the code is accessed to read the data length information stored at the address. This technique is not always efficient because it takes time to access the separate table.
In developing a computer, sometimes two instructions are provided which perform an identical operation on data having different lengths. The technique of directly specifying the data length of each instruction requires a microprogram for each of the two instructions. This increases the required capacity of a ROM for storing the microprograms, thereby increasing an area occupied by the ROM.
The technique of indirectly specifying a data length according to an instruction code need not require two separate microprograms for the two instructions, but a single microprogram can be used which is sufficient to express the two instructions involving two different data lengths. This technique is not applicable, however, to a process such as an interrupt process whose data length cannot be indirectly specified by an instruction code. In this case, a bit having information of the data length must be checked with, for example, an ALU (arithmetic and logic unit) to branch the microprogram. This also increases the area of the microprogram ROM and elongates a process execution state.
A typical arrangement of a conventional information processing apparatus will now be explained with reference to FIG. 1.
In the figure, an information processing apparatus 20 comprises a CPU 10, a microprogram ROM 15, a decoder 16, and a data length specifying circuit 4. The CPU 10 has a plurality of registers 13 and an ALU (arithmetic and logic unit) 14 which are connected to a data bus 11 and an address bus 12. The ALU 14 operates according to microprograms stored in the microprogram ROM 15. The data length specifying circuit 4 is connected to the microprogram ROM 15 and decoder 16 as well as to the ALU 14. The microprogram ROM 15 provides the data length specifying circuit 4 with a directly specified data length output 3. The decoder 16 indirectly specifies the data length of an instruction, for example, byte data and word data, and provides the data length specifying circuit 4 with an indirectly specified data length output 2. The data length specifying circuit 4 specifies one of the directly specified data length output 3 and indirectly specified data length output 2, and provides the ALU 14 of the CPU 10 with a data length output D.sub.out.
For example, two bits of an instruction of a microprogram are used to represent a data length, e.g., "00" for a directly specified data length of eight bits, "01" for a directly specified data length of 16 bits, "11" for a directly specified data length of 32 bits, and "10" for an indirectly specified data length. If the code of an instruction represents any one of the directly specified data lengths, the instruction is executed as it is. If the code represents an indirectly specified data length, the decoder 16 reads the data length of the instruction from a predetermined address in a predetermined table.
Other codes may also be employed. For example, (MOV, A, d, r) for an eight-bit data length, (MOVW, A, d, r) for a 16-bit data length, and (MOVL, A, d, r) for a 32-bit data length may be used.